A Partitioned Translation Lookaside Buffer Approach to Reducing Address Bandwidth

Simulations indicate a simple modification of existing virtual memory hardware can significantly reduce the number of pins required to transmit address information from processor to off-chip memory. This modification consists of partitioning a TLB so that virtual page numbers are stored in a cache on the processor and corresponding real page numbers are stored in registers at the memory, making it possible to transmit a small register index instead of the entire real page number.