A Class of Prefetch Schemes for On-Chip Data Caches

We introduce and evaluate a class of prefetch schemes for on-chip data caches in high-performance RISC processors. These schemes are conservative, initiating a prefetch only when a sequential pattern of references have been observed. Performance results based on traces of five programs in the SPEC suite on an IBM RS/6000 show that these schemes result in a significant reduction in miss ratio without the large increase in memory traffic associated with earlier schemes.