The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator

Hysteresis in a comparator improves the input noise immunity, but can also cause analogue single event transients (ASETs) to be captured. For example, compared to a hysteresis-free comparator, a comparator with a hysteresis voltage of 8 mV, takes an additional 40 ns to recover. As the requirement for noise immunity increases, the vulnerability of a comparator with hysteresis to ASETs worsens. The reliability also worsens for higher sampling frequencies and lower differential input voltage amplitudes. This paper investigates the trade-off between noise immunity and reliability in a 65nm CMOS comparator.