Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time (RT) of ~1.5 s at 85°C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125°C).