A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS

A low power time-to-digital converter (TDC) with high resolution is presented in this paper. The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a phase-prediction technique. A snapshot circuit is used to reduce the sampling rate from digitally-controlled oscillator (DCO) frequency to reference frequency, thus greatly saving power. In addition, the proposed digital architecture adopts a time-amplifier based TDC (TA-TDC) to achieve high resolution. The proposed TDC is implemented in SMIC 40nm CMOS. Simulation results show that it can achieve a resolution about 0.5ps while totally consuming only 163uW.