Low-power design of a 64-tap, 4-bit digital matched filter using systolic array architecture and CVSL circuit techniques in CMOS

A 4-bit 64-chip pseudo noise (PN) coded digital matched filter (DMF) is designed in 0.7 /spl mu/m CMOS technology using a systolic array (SA) architecture. Full-custom and full-static cascode voltage switch logic (CVSL) circuit techniques have been employed in the implementation of the basic building blocks (systoles) of the SA DMF. Significant reduction in number of transistors and power consumption have been achieved. The resultant IC is to be used at the receiver side of a wireless direct sequence spread spectrum (DSSS) communication system.