A high-speed low-power JFET pull-down ECL circuit

An active pull-down output stage that utilizes a composite junction FET (JFET), applied in a high-speed low-power emitter-coupled logic (ECL) circuit, is described. The composite JFET structure is produced by modifying the existing bipolar transistor layout so that a p-channel JFET is formed next to an n-p-n transistor without need of any extra process steps. This p-channel JFET is a four-terminal device: the intrinsic base region defines the channel, the two separate extrinsic bases become the source and drain, the emitter region is the primary gate, and the collector is used as the back gate. The JFET has the same doping profile as the n-p-n bipolar transistor in the intrinsic device region. Simulation results based on a 0.8- mu m double poly-Si, self-aligned bipolar technology indicate that the circuit with a typical loading at a power consumption of 1 mW per gate offers a 24% improvement in the pull-down delay and a 53% improvement in the load driving capability compared with the conventional ECL circuit.<
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