A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates

A compact basic cell for BiCMOS sea-of-gates (SOG) circuits was developed using a bipolar-PMOS merged structure and gate-isolated bipolar transistors. The new cell structure reduces the cell area using the bipolar-PMOS merged transistors. The cell has no restrictions regarding macrocell placement because it has no shared element. The cell density is 60% higher than that of conventional cells. Three types of circuits are provided for a macrocell using the basic cell. The pull-up BiCMOS circuit, one of the circuit alternatives, obtains the shortest gate delay with average load capacitance and high density comparable to a pure CMOS density. The gate delay of 200 ps was achieved with the pull-up BiCMOS two-input NAND gate fabricated with 0.8- mu m BiCMOS technology.<
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