FPGA hardware resources optimization on efficient correlation algorithm for multilevel CSS

In the past few years, the use of Complementary Set of Sequences (CSS) had a considerable impact on several applications, such as: OFDM or quasi-synchronous CDMA communication systems, multiuser active sensing systems, or the development of non-destructive testing (NDT). Their use is attractive due to the ideal aperiodic correlation properties of the sequences. There are efficient architectures to correlate K binary complementary sequences which length is a power of K. One of them has been generalized for its use with a multilevel alphabet, achieving real-valued sequences. In this context, it is possible to generate and correlate sequences with different length than a power of two, avoiding the restrictions in the previous binary architectures about the number and the length of sequences corresponding to a set. In this work, an optimization in terms of hardware resources on the implementation of an efficient multilevel CSS correlator for K sequences is described, where K is a power of two. Therefore, it is possible to generate and correlate sets with more number of sequences or and also with greater lengths. This improves the correlation peak, increasing the robustness to several interferences.