Fused modulo 2n + 1 Add-Multiply unit for diminished-1 operands

Complex arithmetic operations dominate Digital Signal Processing (DSP) applications heavily degrading their performance. Targeting to accelerate the Residue Number Systems-based DSP applications, we optimize the design of the Add-Multiply (AM) operation with modulo 2n + 1 diminished-1 operands by incorporating the direct recoding of the sum of two numbers in its Modified Booth form. Compared to the conventional allocation of an adder and a subsequent multiplier, the proposed fused AM design yields delay, area and power gains.