Experimental Study on Deformation Potential ( ${D}_{{{ac}}}$ ) in MOSFETs: Demonstration of Increased ${D}_{{{ac}}}$ at MOS Interfaces and Its Impact on Electron Mobility

Deformation potential (D
_ac
), which is one of the most important parameters determining the rate of electron-acoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that D
_ac
increases sharply at the MOS interface. To investigate the impact of the increased D
_ac
on μ
_e
, thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that μ
_e
of greater than 1100 cm
²
V
^-1
s
^-1
is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the Dac profile around the MOS interface, experimental μ
_e
of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. μ
_e
of the body-channel SOI MOSFETs is also well reproduced using the same D
_ac
profile. Thus, it is concluded that D
_ac
increases sharply at the Si/SiO
₂
interface. The accurate modeling of the increased D
_ac
around the Si/SiO
₂
interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.