Cu seed optimization for minimum pitch wiring in 10nm and beyond

Technology scaling necessitates interconnect structures (metal and vias) in the back end of the line (BEOL) module to sub 50nm pitch. This presents significant challenges to the conventional metallization scheme, consisting of liner, seed deposition and Cu plating. Seed layer deposition particularly is quite challenged because of increasing aspect ratio. Additionally, the presence of hard mask in the local metal interconnects (Mx) induces undercut in the metal line profile making metallization even more challenging. The consequence is a significant increase in metal voiding defects as compared to previous technology nodes. Hence the conventional metallization scheme requires reengineering to suit the needs of advanced nodes. In this paper, a systematic approach to tune and optimize the copper seed deposition and its effect on metal electrical yield is presented. Through design of experiments (DOE) the metal open yield (post high temperature anneal-hammer test) improved from less than 10% to greater than 50% for the optimized seed deposition recipe (post stress). The optimized recipe reduced the void related defects responsible for the lower metal open yield. Results from current ramp test, via chain yield and electromigration data will be presented for the optimized seed recipe.