Process window discovery methodology development for advanced lithography

With the continued need for shrinking patterning dimensions in semiconductor manufacturing, new lithography techniques, such as advanced multi-patterning, are being introduced into production for 10nm node and beyond, and others, such as EUV, are nearing production requirements. Previous work [1] has shown that these new developments introduce new challenges in terms of qualifying the process window. In the past the boundaries of the overlapping process window (focus and exposure latitude in which all structures in a given layout print within the specifications) were mainly defined by design and OPC related systematic defects and lithographers and defect engineers were relying on Process Window Qualification (PWQ) methods to discover these systematic defects. In more advanced nodes however, the process window is also impacted by FAB related sources (wafer non-uniformity, process variations) or, in case of multi-patterning schemes, also by interactions between the different masks. To take these factors into account PWQ has now evolved into a new methodology called Process Window Discovery (PWD). This paper will focus on further development of this methodology. We will further focus on techniques to enhance the sensitivity of the broadband plasma defect inspection and we will demonstrate how this metrology can highlight intra-field and across-wafer variations. The final step of this work will be to implement this methodology to compare the overlapping process windows of two identical metal layers with 2D logic patterns, of which one layer will be patterned with EUV single patterning and the other will be patterned with 193i triple litho-etch patterning (LE3). For 193i LE3 a special focus goes on the detection of overlay critical hotspots and defining the overlay variation related process window. For EUV special attention goes to EUV specific hotspots and typical sources of variations across wafer.