Data analytics to aid detection of marginal defects in system-level test

As semiconductor feature sizes continue to shrink and outstrip lithography advances, the nature of manufacturing defects has evolved from hard faults to a more subtle lithography-driven form where its impact results in marginal circuit behavior, giving rise to so-called marginal defects. Due to the increasing divergence between test and system modes of operation in complex system-on-chip (SoC) devices, marginal defects can escape production test screen but trigger subsequent failure as the chip operates in the end-system environment. We describe experimental research to probe the nature of marginal defects and develop techniques to expose their signatures in production test. Leveraging the huge investment made in structural-based testing, our novel method applies on-chip-clocked scan patterns under non-destructive stress conditions to obtain delay-informed statistical metric in a fine-grained fashion at numerous device locations, without any hardware modification. Data analytic techniques are used to identify statistical features indicative of marginal behavior which may cause potential in-system failure. Experimental results from a recent mobile SoC product are presented.