PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e
^-8
to 2.8e
^-9
Ωcm
²
, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.