Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level

Early decisions in microprocessor design require a careful consideration of the corresponding performance and reliability implications of transient faults. The size and organization of important on-chip hardware components such as caches, register files and buffers have a direct impact on both the microprocessor resilience to soft errors and the execution time of the applications. In this paper, we employ a state-of-the-art x86-64 full-system micro-architectural simulator and a comprehensive fault injection framework built on top of it to deliver a detailed evaluation of the reliability and performance tradeoffs for major hardware components across several important parameters of their design (size, associativity, write policy, etc.). We also propose a simple and flexible fitness function that measures the aggregate effect of such design changes on the reliability and the performance of the studied workload.