Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

In this letter, we propose a layer selection method by permutations (LSMPs) of string select line (SSL) bias and string select transistor with multi-level states. Due to the increased number of threshold voltage orderings by the permutation, the number of required SSLs for the layer selection and the space occupied by SSLs can be minimized. Also, the operation scheme for the layer selection is discussed. To verify the operation of proposed LSMP, a fabricated pseudo-LSM is measured. As a result, it is clearly revealed that the number of selectable layer can be increased drastically by the LSMP.