An 8-bit CMOS 3.3-V 65-MHz digital-to-analog converter with a symmetric two-stage current cell matrix architecture

This paper describes a 3.3-V-65-MHz 8-bit CMOS digital-to-analog converter (DAC) with two-stage current cell matrix architecture which consists of a 4-MSB and a 4-LSB current matrix stage. The symmetric two-stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the number of high swing cascode current mirrors. The designed DAC with an active chip area of 0.8 mm/sup 2/ is fabricated by a 0.8-/spl mu/m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and integral nonlinearity/differential nonlinearity (INL/DNL) are 6 ns, 16 ns, and less than 0.8 LSB, respectively. The designed DAC is fully operational for the power supply down to 2.0 V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3 V is measured to be 34.5 mW.