Investigation of embedded silicon germanium typical defect solution for advanced CMOS process

Embedded silicon germanium (e-SiGe) technology in PMOS source/drain area is a trend for advanced CMOS process development. Especially when device gate length reach 28nm or below, sigma shaped trench in PMOS S/D area along with higher germanium and boron concentrations in the SiGe film are needed to improve PMOS channel hole mobility and device Ion/Ioff performance. However, selective epitaxy of SiGe:B will be increasingly challenging as germanium and in-situ boron concentrations increase. The biggest problem is the ball defect showing up after selective epitaxy SiGe processes, which is one of the major killers for device yield. In this paper, we investigated the impact of different wet clean and selective epitaxy conditions on SiGe process defects. For the wet clean experiment, one additional clean step was added to clean the wafer surface after dry etch & wet etch to form the sigma shape trench, followed by chemical to removal of native oxide followed by SiGe: B process. This way we can get best ball defect performance. For selective epitaxy process, seed, bulk & cap layers condition were adjusted. Finally, we found that the cap layer is the most significant factor that could produce SiGe ball defect. By SiGe ball defect reduction, device yield performance has a great improvement.