A high speed low power negative sensing architecture for 3D NAND Flash memory

A new sensing architecture aiming at negative threshold voltage detection for 3D NAND Flash memory cells is proposed. This sensing architecture does not need triple well devices and negative voltage supplies. In this architecture, we apply 2 V to source line (SL) rather than 0V which is always used in conventional method. We prove that this architecture is feasible by Technology Computer Aided Design (TCAD) simulation. We have also designed a sense amplifier (SA) to support the proposed sensing architecture. This SA has advantages including lower noise, 9.4% faster read speed, and 51.6% lower power consumption compared to the conventional counterpart.