Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs

We demonstrate new fabrication technologies for dual-gate CMOSFETs with multiple-thickness gate oxide. The process consists of two major parts: forming a multiple-thickness gate oxide by using Ar/sup +/ and N/sup +/ implantation, and impurity doping into dual-gate poly-Si by using self-aligned thermal oxidation. During the doping process, nitrogen distribution recoiling from a Si/sub 3/N/sub 4/ on a PMOSFET gate suppresses boron penetration.