Shallow trench isolation for advanced ULSI CMOS technologies

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space. The trench bottom is rounded to minimize stress. (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area. (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 0.16 /spl mu/m wide trenches free of voids. Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions. Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage. (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback. (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance.