A compact SOI-MOSFET model for high temperature circuit simulation with emphasis on process and layout data

In this paper we present a C/sub /spl infin//-continuous compact SOI-MOSFET model that is applicable to circuit simulation. Unlike previously published models we accurately model the transition between fully depleted and partially depleted operating regions as it depends on frontgate and backgate voltages. The new model allows a wide range of biasing due to the accurate description of back accumulation and back inversion. A novel 2D coupling approach to solve Poisson's equation in the x-y-plane enhances the description of the short channel effects DIBL, DICE and charge sharing. A two dimensional formulation of the transport equation in the y-z-plane makes it possible to model split-source body-tied transistors in a wide range of device geometries with only one single set of parameters. We show that our model offers an exceptional predictive ability up to a temperature of 300/spl deg/C due to the physical meaning of the relationships employed.