Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA

This paper presents a study of different implementations of arithmetic operations on FPGAs. Radiation vulnerability has been analyzed for each implementation using the fault injection platform NESSY. Results in terms of area, delay and reliability are presented. We propose to build a library of HDL templates taking into account the performed tests. This library is used during the design process with a synthesis tool that implements digital circuits as reliable as possible. Experimental results show that implementations using DSP slices are the ones which achieve better results.