Pre-bond testing of the silicon interposer in 2.5D ICs

In interposer-based 2.5D integrated circuits, the passive silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient method to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. In order to reduce test time, the concept of weighted critical area is defined and utilized. We present HSPICE simulation results to demonstrate the effectiveness of the pre-bond test solution. The benefit of using weighted critical area is demonstrated using a commercial interposer from GLOBALFOUNDRIES.