System level synthesis for virtual memory enabled hardware threads

Newly introduced ARM-based FPGA platforms enable transparent hardware/software multithreading by providing cache-coherent memory accesses to hardware accelerators. However, the lack of support for virtual memory on the accelerator side hinders the use of off-the-shelf software stacks, such as offered by a Linux-based system, which limits their applicability in a legacy environment. To address this problem, we propose a fully automated high-level synthesis-based source-to-source flow to efficiently support virtual memory in hardware accelerators.