A 24- $\mu \text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS

This paper presents an energy-efficient 12-bit successive approximation (SA) register analog-to-digital converter (ADC) for high-performance sensor systems. The ADC uses a two-step decision digital-to-analog converter (DAC) switching scheme for improving the DAC linearity with small capacitor arrays. The scheme effectively eliminates the largest binary DAC middle-code transition glitch. The proposed switching scheme also tolerates DAC settling errors during SA. Avoiding unnecessary DAC switching error improves the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR). A reference-scaling binary capacitor DAC is used for improving the ADC energy efficiency without sacrificing production reliability. The implemented prototype in 0.11-μ CMOS occupies an active area of 0.097 mm
²
. At 1 MS/s, it consumes a total power of 24 μ from a 0.9 V supply. The measured differential nonlinearity and the integral nonlinearity are 0.4 least significant bit (LSB) and 0.7 LSB, respectively. Among 50 chips, the peak measured SNDR is 68.3 dB. The peak and the average of SFDR are 89 and 83.5 dB, respectively. The optimal effective number of bits is 11 bit at the Nyquist-rate input, which is equivalent to a figure of merit of 11.7 fJ/conversion-step.