A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands

This brief delineates the design and realization of a 10-GS/s 4-bit digital-to-analog converter (DAC) for the cognitive ultrawideband (CUWB), an emerging solution for low interference and efficient spectrum utilization in communication networks. The DAC serves as the data converter for the adaptive waveform transmitter therein, largely to reduce its power dissipation and hardware complexity. For reasons of low power dissipation and low-cost CUWB application, the resolution of the DAC is 4 bits, its realization is in standard 65-nm CMOS, and the architecture is a single core. The binary current-steering DAC includes critical building blocks such as current sources and a novel deglitcher circuit. The current sources are designed for small area with high linearity based on our derived relationship between current-source output resistance and linearity parameters [integral nonlinearity (INL) and spurious-free dynamic range (SFDR)]. The deglitcher design includes high-speed source followers as high-speed low voltage swing buffers to improve the linearity by decreasing the output glitch energy. The DAC embodies an in situ hardware efficient (small integrated-circuit area and reduced input/output pinout) tester that generates 4 × 10-Gb/s test-data pattern to facilitate functional verification. The designed DAC achieves ≤ 0.16-least significant bit INL/differential nonlinearity and > 23-dBc SFDR over the Nyquist bandwidth up to 4.53 GHz, and features the most competitive figures-of-merit of all similar DACs reported to date.