Author’s Reply to “Comments on ‘Optimization of a Compact I–V Model for Graphene FETs: Extending Parameter Scalability for Circuit Design Exploration’ ” S. Frégonèse and T. Zimmer

We appreciate the careful analysis and comments by Frégonèse and Zimmer, where they show that the model proposed, accurately reproduces experimental data from graphene FETs (GFETs) when an appropriate smoothing factor is used. The authors have proposed an extension of this model by Frégonèse et al. with an exact calculation of a denominator. We compared the model extension with the original work. Unfortunately, we did not use a suitable smoothing factor in our comparison, which lead to a strong artifact in the calculations and was absent in the exact solution. Following the argument, the authors agree with our colleagues that there is no artifact at the Dirac point in their GFET compact-model when a proper smoothing factor is used. We were not aware of the requirement of such a factor in specific cases when implementing the model because it is not mentioned; therefore, we apologize for misrepresenting their work.