Improving synthesis of fixed-point adders on FPGAs using primitive instantiations

Whilst the pre-fabricated aspects of FPGAs have many advantages, the fixed nature of the underlying fabric limits the optimized synthesis of arithmetic circuits on these platforms. Many adder architectures, that suit ASICs have been implemented using FPGAs and it has long been established that for FPGAs the ripple carry adder gives the best performance in terms of speed and resource utilization. This is mainly due to the inherent dedicated carry-chain logic that by-passes the general FPGA routing and speeds up the carry propagation. Conventional intuition has it that the best performance with FPGAs is achieved by designing arithmetic circuits through inferential coding, where the synthesis tool infers the design from the general hardware description language. The inferred logic is then mapped onto the underlying resources where the synthesis tool uses its inherent design strategies that are driven by specific optimization goals (area or speed). Evidently most of the prior work uses inferential coding for designing arithmetic circuits. In this paper, however, we experimentally show that direct instantiations of FPGA primitives could lead to improved synthesis results. This involves restructuring of the initial Boolean network prior to the design entry. Proper restructuring ensures an efficient utilization of the underlying fabric which is achievable only through direct instantiation of the in-built FPGA primitives. Our implementation targets Virtex-5 FPGA family from Xilinx. The analysis shows a 7 to 20 percent improvement in critical path delay and 70 to 90 percent improvement in on-chip resource utilization as the operand word-length is varied from 8 to 64 bits.