9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue

Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current IREAD compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9× higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1×/2.1×/4.9× lower hold power H
_Power
during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5×/4.3×/1.25× narrower spread (i.e., more reliable) in IREAD/RSNM/H
_Power
compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17×/1.17×/1.25× longer write delay compared with FD8T/UDVS10T/SEDF9T.