A novel 3D pixel concept for Geiger-mode detection in SOI technology

In this paper, a novel SPAD architecture implemented in Silicon-On-Insulator (SOI) CMOS technology is proposed. Thanks to its intrinsic 3D structure, the proposed solution is expected to allow very small pixels while enabling a very high fill factor. Furthermore, the pixel read-out electronics as well as the whole detector electronics can benefit of the well-known advantages brought by SOI technology with respect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations based on realistic process parameters provided by the foundry are carried out in order to optimize and validate the avalanche diode architecture for an optimal electric field distribution in the device and to obtain a first order estimation of the main parameters of the SPAD, such as the breakdown voltage, the avalanche triggering probability and the dark count rate.