Scaling/LER study of Si GAA nanowire FET using 3D Finite Element Monte Carlo simulations

ID-VG characteristics of a 22 nm gate length gate-all-around (GAA) Si nanowire (NW) obtained from a 3D Finite Element (FE) Monte Carlo (MC) in-house simulation toolbox which uses anisotropic 2D Schrödinger equation based quantum corrections (SEQC) are compared against experimental data with excellent agreement at both low and high drain biases. We then scale the Si GAA NW according to the ITRS specifications to a gate length of 10 nm predicting that the scaled NW will ensure a required on-current of above 1mA/μm and superior electrostatic integrity of a nearly ideal sub-threshold slope of 66 mV/dec and a DIBL of 39 mV/V. The effects of nanowire (NW) line-edge roughness (LER) on threshold voltage and off-current are investigated by calibrated 3D FE quantum corrected (QC) drift-diffusion (DD) toolbox.