A mixed-level power estimator for CMOS circuits using pattern compaction techniques

This paper presents a novel methodology for the average power estimation. According to the power information obtained from logic-level simulation, we first perform pattern compaction and derive the relative weighting factors, and then perform accurate transistor-level power simulation by using the compact sequence. Combining both the weighting factors and the accurate power dissipation data, we calculate and report the estimated average power dissipation. Finally, we verify our method by using some practical industrial design examples with their functional simulation patterns. The experimental results show that our approach could speed up to two orders of magnitude without losing too much accuracy.