A fast-locking digital delay line with duty-conservation

A two-clock-cycle locking and duty-conserving digital delay line is presented. The proposed delay line has a new matching detection circuit which can decide the tapping position within the detecting resolution range of 0.3 ns. The proposed delay line has duty-conserved 2-clock-cycle locking time at the frequency range of 70-180 MHz using 0.5 /spl mu/m CMOS process.