A circuit partitioning algorithm under path delay constraints

This paper presents a timing-driven circuit partitioning algorithm for the general delay model. The proposed algorithm consists of the clustering and iterative improvement phases. In the first phase, we reduce the problem size, that is the size of a given graph, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the Fiduccia and Mattheyses algorithm is applied and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.