LV/LP CMOS high speed analog multiplier

In this paper we propose a new LV/LP four quadrant analog multiplier. The multiplier is composed of a LV/LP CMOS composite cell with two high input impedance terminals (LVLPCCC) which has a square-law current-voltage characteristic. SPICE simulation results using MOSIS 2 /spl mu/m n-well process parameters show that the multiplier achieves a maximum differential input voltage of 2V/sub pp/, f/sub -3 dB/ of 250 MHz and power consumption of 1.17 mW with a 3 V supply. Also, simulated Total Harmonic Distortion (THD) less than 1% at frequency up to 8 MHz for 2 V/sub pp/ input voltage is obtained.