A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop

In phase locked loops, settling time and tuning range form important performance parameters, in addition to jitter and power consumption. However, most PLLs are designed for improvement only in jitter and power, thus resulting in longer settling time. This work proposes an offset-frequency based fractional-N DPLL for generating frequency in the range of 4.7 GHz-5 GHz. The proposed PLL employs (i) hybrid phase detection with different TDC blocks to avoid the need of improving the TDC resolution for low jitter, (ii) a state machine using differential and double integration filtering effect for fast locking in the final stage of settling, and (iii) an infinite delay range DTC wherein the resolution of fractional frequency could be controlled independent of the loop bandwidth. The PLL is implemented in 65nm CMOS-LL technology and is able to achieve a competitive performance with 1.5μs settling time, 1.7ps jitter and power consumption of 25mW.