Digital oscillation-test method for delay and stuck-at fault testing of digital circuits

Testing delay faults is becoming critical in new deep submicron digital circuits. This paper introduces a new technique for delay and stuck-at fault testing in digital integrated circuits. The proposed technique consists of sensitizing a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all or at least critical paths in the circuit. To establish oscillations, we should make sure that there is an odd number of inverters in the loop. This technique can be used along with scan techniques or be implemented as a built-in self-test technique. Benchmark results confirm the efficiency of the proposed technique. The technique has been implemented in practice for an an 8-bit digital adder on a field programmable device.