Defect-oriented test quality assessment using fault sampling and simulation

The purpose of this paper is to present a novel methodology for the estimation of VLSI products defect level, or reject rates, in the IC design environment. A new defect-oriented (DO) fault extraction and stratified sampling technique, implemented in an extraction tool, lobs, is used with a novel DO fault simulation tool, veriDOFS, which uses a commercial Verilog simulation tool. The proposed methodology allows the evaluation of DL values with limited confidence intervals, using reduced fault samples. Results, for a s38417 benchmark circuit (almost 100,000 transistors and over 140,000 extracted bridging defects) lead to test quality validation with 2,000 sampled faults.