60-GHz CMOS Current-Combining PA With Adaptive Back-Off PAE Enhancement

This brief describes the design and implementation of a current-combining power amplifier (PA) with a fully adaptive approach to enhance the output power and the back-off power added efficiency (PAE). The PA consists of a main amplifier and an auxiliary amplifier. Adaptive biasing technique is employed to shut down or provide optimum bias voltage to the auxiliary amplifier according to the input power level. The 50-Ω input matching is realized with adaptive power distribution. The output load modulation is accomplished by a compact output matching network (MN) using transmission lines and transformers. Based on the same MN, the back-off PAE degradation caused by the low output impedance of the auxiliary path is mitigated. The proposed PA is designed at 60 GHz using 65-nm CMOS and is experimentally characterized. The measurement results reveal 16-dBm OP1dB and 14% peak PAE. Approximately 8% PAE at 6-dB back-off is achieved, addressing improved back-off efficiency.