27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS

Integration of low-power and area-efficient ADCs is a key differentiator in modern mixed-signal SoCs. In scaled technologies, power challenges have been addressed using SAR architectures, often in combination with techniques like redundancy, asynchronous operation, and time interleaving to meet the application sampling rate requirements. However, for high-resolution ADCs (9b+ ENOB), a traditional SAR is intrinsically energy-inefficient since it reuses the same low-noise comparator to perform both coarse conversions (where little accuracy is needed) and fine conversions (where thermal noise is of paramount importance). This is addressed in [1,2] with hybrid SAR-pipeline architectures that employ SAR as subADCs, but whose noise performance is determined by a high-efficiency interstage amplifier as opposed to the comparator.