24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm

Matrix multiplication, enabled by multiply-and-accumulate hardware, is ubiquitous in signal processing, computer graphics, machine learning, and optimization. Many important applications with inherent robustness to reduced precision for matrix multiplication, e.g. inference for neural networks [1], can take advantage of analog signal processing for energy efficiency. This work presents a 64-cycle programmable passive Switched-Capacitor Matrix Multiplier (SCMM) with co-designed bitline-less memory. The design exploits 300aF unit fringe capacitors for high speed and low energy charge-domain processing and contains the input DAC, multiply-and-accumulate SAR ADC, and local memory. Two applications of the SCMM are demonstrated: 1) an analog front-end for an image classifier system, which reduces A/D conversions by 21x and multiply-and-accumulate compute energy by 11x over a conventional system, and 2) a co-processing accelerator to solve Stochastic Gradient Descent optimization, which achieves a measured 7.7 TOPS/W at 2.5GHz.