A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI

A novel inverse-T LDD (ITLDD) CMOS process has been developed as part of a submicron CMOS technology that features self-aligned LDD/channel implantation for improved hot-carrier protection. The resulting ITLDD device structures can be designed with very light n- and p-LDD (lightly doped drain) implantations. This leads to lower substrate current due to reduced compensation effects of the lightly doped LDD regions by the heavy channel doping profile. The use of selective polysilicon deposition rather than an incomplete polysilicon etchback process to define the inverse-T gate results in a simpler, more manufacturable process for the ITLDD structure.<
>