New Multiport I/O Model for Power-Aware Signal Integrity Analysis

This paper presents a new multiport power-aware behavioral model formulation and extraction for high-speed input/output (I/O) buffers that enable the transient prediction of power and ground bouncing effects under simultaneously switching output (SSO) buffers for signal and power integrity evaluation. The derivation of the proposed model is based on the analysis and extension of the I/O buffer information specification (IBIS) buffer issue resolution documents (BIRDs) (i.e., BIRD-95.6 and BIRD-98.3) and the macromodeling via parametric identification of logic gates (Mpilog) (i.e., artificial neural network). The analysis of the previous IBIS and Mpilog modeling approaches is followed by a new model formulation that integrates both the previous BIRDs with a well-designed characterization and parametric extraction procedure. The accuracy and computational performances of the proposed model is evaluated under a realistic SSO scenario.