Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits

This brief presents a high-speed inductorless D flip-flop (DFF) architecture that works on the principle of equalization using two feedbacks. Feedback from the first latch output to the input effectively results in a linear equalizer, whereas the feedback of the flip-flop output to the input culminates in decision feedback equalization. The proposed feedback-based DFF designed in a 90-nm CMOS technology shows 37.5% improvement in speed, as compared with the conventional flip-flops (conv-DFFs) without feedbacks. Post-layout circuit simulations also show an overall 33.7% improvement in the speed of a high-speed pseudorandom binary sequence generator when such feedbacks are added to conv-DFFs in it. Additionally, when this technique is used in a Hogge phase detector for clock and data recovery, 89% improvement in vertical eye opening and 73% reduction in pattern-dependent jitter at the input of the phase detector are observed. In essence, the technique effectively achieves distributed equalization in high-speed communication circuits.