Design and implementation of the ctrie-hash algorithm for fast routing lookup

The rapid development of IP networks requires high performance routers. The fast routing lookup engine in routers is a key problem to achieve higher throughput. In this paper, we present a new high performance IP lookup scheme combining path-compressed binary trie, hash algorithm and address aging technique. It can meet the search requirements of more than 10Gbps data stream and consumes less hardware resources. The design is implemented in Xilinx xc4vsx55 field programmable gate array (FPGA) and can perform 20 million lookups per-second with a 100MHz system clock and occupies only 3018 4-input LUTs.