Gate-All-Around In0.53Ga0.47As Junctionless Nanowire FET With Tapered Source/Drain Structure

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (L
_CH
), NW height (H
_NW
), and NW width (W
_NW
) were realized. Despite having a large equivalent oxide thickness of ~4.5 nm, high extrinsic transconductance (G
_m,ext
) of 820 μS/μm was achieved at V
_D
of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (R
_SD
) of 275 Ω · μm, which is one of the lowest among the reported 3-D InGaAs MOSFETs.