Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration

The high power and the long global interconnect delay are two of the major bottlenecks that limit the further scaling down of the process nodes in the VLSI systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and the interconnect delay. Current-induced magnetic domain-wall (DW) racetrack memory (RM) has the advantages of nonvolatility, fast switching speed, and high density. It may offer opportunities to open a new paradigm of circuits and architectures to significantly alleviate the power and delay issues. This paper presents the magnetic DW RM-based new nonvolatile logic designs for the low-power computing and fast run-time-reconfiguration. Both data transfer and reconfiguration are achieved by shifting the magnetic strips. Verify-before-shift approach is used to greatly reduce the shifting energy. Compared with the conventional nonvolatile logic gate, the proposed nonvolatile logic scheme doubles the operating speed with 87% lower operating energy. Moreover, the proposed nonvolatile logic gates can be reconfigured after fabrication, which makes the designs more flexible and robust. The reference reconfiguration and the polarity reconfiguration are presented in this paper, which can be finished in 1 ns with 130 fJ/strip energy and 6 ns with 390 fJ/strip energy, respectively.