Quasi-Static Terminal-Charge Model for Symmetric Double-Gate Ferroelectric FETs

Symmetric double-gate ferroelectric FETs (SDG-FeFETs) have better short-channel electrical behavior and hold promise in reducing the subthreshold swing below the classical Boltzmann's limit. Surface potential and drain current models for SDG-FeFETs have already been published in the literature. In this paper, we derive the quasi-static terminal-charge models for these devices, which can be seamlessly integrated into standard circuit simulators using the Verilog-A interface. The terminal-charge models proposed are shown to match very well with exact numerical integration of Ward-Dutton terminal-charge integrals, for all bias conditions. Core compact model for the SDG-FeFET is implemented in a SPICE circuit simulator, and the simulation of different circuits built using SDG-FeFET transistors shows improvement in their switching behavior.